1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor and a method of fabricating the same. Although the present invention is suitable for a wide scope of application, it is particularly suitable for improving a performance of the semiconductor device and for reducing a power consumption.
2. Discussion of the Related Art
The background art will be explained with reference to FIG. 1 illustrating a logic circuit diagram of a two-input NAND gate. As shown in FIG. 1, a NAND gate includes first and second PMOS transistors 1 and 2 connected in parallel and first and second NMOS transistors 3 and 4 connected in series.
Source terminals of the PMOS transistors 1 and 2 are in common connected to a power source voltage terminal Vdd. First and second input signals are applied to respective gate electrodes. A drain terminal of the PMOS transistors 1 and 2 is used as a common output terminal of the first and second PMOS transistors 1 and 2. The common drain terminal of the first and second PMOS transistors 1 and 2 connected with a drain terminal of the first NMOS transistor 3. The first input signal is applied to a gate electrode of the first NMOS transistor 3. A source terminal of the first NMOS transistor 3 is connected with a drain terminal of the second NMOS transistor 4. The second input signal is applied to a gate electrode of the second NMOS transistor 4. A source terminal of the second NMOS transistor 4 is connected with a ground voltage terminal Vss.
In the aforementioned NAND gate, a probability for outputting an value of 1" by combining the first and second input signals is three-fourth whereas a probability is one-fourth for outputting an value of 0". Therefore, if both the first and second input signals are 1", the output value is 0". If not, the output value is 1".
In addition, since the first and second NMOS transistors 3 and 4 are connected in series, a pull-down path resistance is increased. Consequently, to keep the pull-down path resistance the same, a size of the NMOS transistor should be the same as that of the PMOS transistor.
FIG. 2 is a logic circuit diagram illustrating a background art two-input NOR gate. As shown in FIG. 2, a NOR gate includes first and second PMOS transistors 5 and 6 connected in series and first and second NMOS transistors 7 and 8 connected in parallel.
A source terminal of the first PMOS transistor 5 is connected to a power source voltage terminal Vdd. A first input signal is applied to a gate electrode of the first PMOS transistor 5. A source terminal of the second PMOS transistor 6 is connected to a drain terminal of the first PMOS transistor 5. A second input signal is applied to a gate electrode of the second PMOS transistor 6. A drain terminal of the PMOS transistor 6 is used as an output terminal. Drain terminals of the first and second NMOS transistors 7 and 8 are in common connected to the drain terminal of the second PMOS transistor 6. The first and second input signals are applied to respective gate electrodes of the first and second NMOS transistors 7 and 8. Their source terminals are connected to a ground voltage terminal Vss.
In the aforementioned NOR gate, a pull-up path is formed by a serial connection between the first and second PMOS transistors 5 and 6 whereas a pull-down path is formed by a parallel connection between the first and second NMOS transistors 7 and 8. A probability for outputting an value "1" by combining the first and second input signals is one-fourth while a probability is three-fourths for outputting "0". Therefore, if both the first and second input signals are "0", an output value is "1". If one of the input signals is "1", an output value is "0".
Meanwhile, since a serial connection between the first and second PMOS transistors 5 and 6 increases a pull-up path resistance, a symmetric switching may be executed only if a size of the PMOS transistor is four times greater than that of the NMOS transistor.
A background art semiconductor device and a method of fabricating the same will be described with reference to the accompanying drawings.
FIG. 3 is a cross-sectional view illustrating two NMOS transistors according to the background art, connected in series in the logic circuit of the NAND gate of FIG. 1.
As shown in FIG. 3, NMOS transistors include a field oxide film (not shown) formed in a field region of a semiconductor substrate 11 where the field region and an active region are defined, first and second gate electrodes 13a and 13b formed in a predetermined region on the active region at a predetermined interval by forming gate insulating films between the semiconductor substrate 11 and the first and second gate electrodes 13a and 13b, insulating film sidewalls 16a formed at both sides of the first and second gate electrodes 13a and 13b, and first, second and third heavily doped n-type impurity regions 17a, 17b, and 17c each having an lightly doped drain (LDD) region formed in the surface of the semiconductor substrate 11 at both sides of the first and second gate electrodes 13a and 13b.
FIGS. 4A to 4E are cross-sectional views illustrating the process steps of fabricating method of two NMOS transistors connected in series in the logic circuit of the NAND gate of FIG. 1.
As shown in FIG. 4A, a field oxide film (not shown) is formed at a field region of a semiconductor substrate 11 where the field region and an active region are formed. A gate insulating film 12 and a polysilicon layer 13 for a gate electrode are sequentially formed on the active region of the semiconductor substrate 11. Subsequently, a photoresist 14 is coated on the polysilicon layer 13 and then selectively patterned by exposure and developing processes.
As shown in FIG. 4B, the polysilicon layer 13 and the gate insulating film 12 are selectively removed using the patterned photoresist 14 as a mask to form first and second gate electrodes 13a and 13b.
Referring to FIG. 4C, the photoresist 14 is removed from the first and second gate electrodes. Then, n-type impurities is implanted into the entire surface of the semiconductor to form a LDD region 15 in the semiconductor substrate 11 at both sides of the first and second gate electrodes 13a and 13b using the first and second gate electrodes 13a and 13b as masks.
As shown in FIG. 4D, an insulating film 16 is formed on the entire surface of the semiconductor substrate 11 including the first and second gate electrodes 13a and 13b.
In FIG. 4E, the insulating film 16 is etched back to form insulating film sidewalls 16a at both sides of the first and second gate electrodes 13a and 13b. Subsequently, n-type impurities are implanted into the entire surface of the semiconductor substrate 11 using the first and second gate electrodes 13a and 13b and the insulating film sidewalls 16a as masks in order to form first, second and third heavily doped n-type impurity regions 7a, 17b and 17c. The first, second and third heavily doped n-type impurity regions 17a, 17b, and 17c are connected to the LDD region 15.
A process steps of fabricating method of two PMOS transistors connected in series in the logic circuit of the NOR gate of FIG. 2 are identical to the above process steps except that a p-type impurity implantation process is performed instead of a n-type impurity ion implantation process.
The background art semiconductor device and the method of fabricating the same have several problems as follows.
Since two transistors connected in series have the same structure, a leakage current in turn-off state increases when a low power operation, thereby increasing a power consumption.
In addition, when a threshold voltage is increased to prevent a power consumption, a driving current is reduced in operating state, thereby reducing an operation speed of the transistor.
Further, it is impossible to eliminate a leakage current in off state by applying a voltage to the substrate at a low threshold voltage since the substrate has a low doping concentration.